Block-level verification has become a fairly mature technology over the past 10 years. All of the major EDA players support constrained-random stimulus generation in the simulation testbench. As part ...

Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex ...

There are three aspects to verification. As an industry, how we balance these aspects has led to a quality crisis, wrapped in a debug loop, inside a constrained random test. It’s time for a ...

If verification were as hot a topic as artificial intelligence (AI), we would be measuring things like effective verification cycles per watt. Unfortunately, the only things that ever seem to be ...

New research paper titled “Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification” from researchers at University of Bristol and Infineon Technologies. “Constrained ...