Over the last twenty years, structural testing with scan chains has become pervasive in chip design methodology. Indeed, it’s remarkable to think that most electronic devices we interact with today ...

The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules. Hierarchical DFT divides the design into smaller pieces, creates test ...

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Density functional theory (DFT) calculations have become a ubiquitous feature of journal articles in all of chemistry’s subdisciplines, used by researchers to electronically characterize molecules or ...

If you used every particle in the observable universe to do a full quantum simulation, how big would that simulation be? At best a large molecule. That’s how insanely information dense the quantum ...

This is the second part of a two-part discussion (Part 1 appeared in August) in which the author considers fault-coverage analysis and simulation for full-scan testing of ASIC designs. These elements ...

Designing surfaces that precisely control how light behaves at the nanoscale is tricky. Optical Fourier surfaces, which are nanostructured gratings that redistribute light into specific directions and ...

What is CTL, and why is it important to the semiconductor industry? The answers are here. Although the IEEE 1450.0 Stand-ard Test Interface Language (STIL) was adopted in March 1999, widespread ...