EDN

Flash and Logic Process Integration

Spansion Inc. and United Microelectronics Corporation announced the joint development of a 40nm process that integrates UMC’s 40nm LP logic process with Spansion® proprietary embedded Charge Trap (eCT ...
Electronic Design

Could This “2D” Transistor Process Transform Logic and Power Device Production?

CDimension’s technology, which enables semiconductor makers to manufacture arrays of extremely small, fast, and efficient “2D” transistors, has the potential to change what’s possible for both digital ...
Design-Reuse

Virage Logic First to Deliver Complete Memory Compiler and Logic Library IP Portfolio for TSMC 40nm Process

SiWare Physical IP Provides Built-in Power Management Capabilities to Meet Tight Power Budgets FREMONT, Calif.-- April 07, 2008 --Virage Logic Corporation, the semiconductor industry’s trusted IP ...
Design-Reuse

Samsung Reportedly Moves Custom HBM Logic Die to 2nm Foundry Process for the First Time

Samsung is stepping up its development of custom HBM logic dies. According to ZDNet, sources say the company is designing logic dies for custom HBM using foundry process nodes as advanced as 2nm. The ...