GitHub

mariusmm/RISC-V-TLM

This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2. It supports RV32IMAC and RV64IMAC Instruction set.
Design-Reuse

Open SystemC Initiative Advances IP Interoperability and Reuse with New Draft Standard for Transaction-Level Modeling

SystemC users urged to provide feedback on TLM-2 Draft 2 by January 31st SAN JOSE, Calif. December 4, 2007 The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to ...
EDN

OSCI issues new TLM standard

Venice, Florida &#8212 The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC TM as an industry standard language for electronic ...
IEEE

Tutorial: Full System Simulation with SystemC TLM-2.0 and the Arm Fast Models

Abstract: This tutorial focuses on loosely-timed full systems simulation (Virtual Prototyping) that is widely adopted in industry for software development and verification use cases due to its ...