This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to ...
Run yosys -o foo.blif -S ./yosys_rocket/*.v (zipped rocket chip generated verilog here: yosys_rocket.zip). Segfault in "7.17. Executing MEMORY_MAP pass": [...] // lots of lines removed 7.16.10.
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